forked from aniani/vim
Runtime file updates.
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@@ -1,10 +1,12 @@
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" Language: Verilog HDL
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" Maintainer: Chih-Tsun Huang <cthuang@larc.ee.nthu.edu.tw>
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" Last Change: 2011 Dec 10 by Thilo Six
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" URL: http://larc.ee.nthu.edu.tw/~cthuang/vim/indent/verilog.vim
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" Maintainer: Chih-Tsun Huang <cthuang@cs.nthu.edu.tw>
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" Last Change: 2017 Feb 24 by Chih-Tsun Huang
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" URL: http://www.cs.nthu.edu.tw/~cthuang/vim/indent/verilog.vim
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"
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" Credits:
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" Suggestions for improvement, bug reports by
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" Takuya Fujiwara <tyru.exe@gmail.com>
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" Thilo Six <debian@Xk2c.de>
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" Leo Butlero <lbutler@brocade.com>
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"
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" Buffer Variables:
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@@ -38,7 +40,7 @@ function GetVerilogIndent()
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if exists('b:verilog_indent_width')
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let offset = b:verilog_indent_width
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else
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let offset = &sw
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let offset = shiftwidth()
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endif
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if exists('b:verilog_indent_modules')
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let indent_modules = offset
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