PnR Messages

Report Title PnR Report
Design File /Users/car/Projects/hope/hope/impl/gwsynthesis/hope.vg
Physical Constraints File /Users/car/Projects/hope/tangnano20k.cst
Timing Constraints File /Users/car/Projects/hope/tangnano20k.sdc
Tool Version V1.9.11.03 Education
Part Number GW2AR-LV18QN88C8/I7
Device GW2AR-18
Device Version C
Created Time Fri Feb 20 01:45:30 2026
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.029s, Elapsed time = 0h 0m 0.026s Placement Phase 1: CPU time = 0h 0m 0.092s, Elapsed time = 0h 0m 0.087s Placement Phase 2: CPU time = 0h 0m 0.057s, Elapsed time = 0h 0m 0.054s Placement Phase 3: CPU time = 0h 0m 0.305s, Elapsed time = 0h 0m 0.299s Total Placement: CPU time = 0h 0m 0.483s, Elapsed time = 0h 0m 0.466s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.049s, Elapsed time = 0h 0m 0.05s Routing Phase 2: CPU time = 0h 0m 0.357s, Elapsed time = 0h 0m 0.317s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.367s Generate output files: CPU time = 0h 0m 0.987s, Elapsed time = 0h 0m 0.958s
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1416MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1196/20736 6%
    --LUT,ALU,ROM16 1124(1091 LUT, 33 ALU, 0 ROM16) -
    --SSRAM(RAM16) 12 -
Register 142/15750 <1%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 136/15552 <1%
    --I/O Register as Latch 0/198 0%
    --I/O Register as FF 6/198 4%
CLS 702/10368 7%
I/O Port 10/66 16%
I/O Buf 9 -
    --Input Buf 2 -
    --Output Buf 7 -
    --Inout Buf 0 -
BSRAM 8 SP
1 pROM
 20%
DSP 1 MULT36X36
9%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/80%
bank 1 2/923%
bank 2 0/40%
bank 3 1/176%
bank 4 0/80%
bank 5 0/100%
bank 6 6/967%
bank 7 1/1100%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 1/8 13%
GCLK_PIN 0/5 0%

Global Clock Signals:

Signal Global Clock Location
i_clk_d PRIMARY TR BR BL
addr_registers[0]_ER_init LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
i_clk - 4/7 Y in IOL7[A] LPLL1_T_in LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
i_rst_n - 88/3 Y in IOR30[A] MODE0 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
i_uart_rx - 70/1 Y in IOT44[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
o_uart_tx - 69/1 Y out IOT50[A] - LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
o_led[0] - 15/6 Y out IOL47[A] LPLL2_T_fb LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
o_led[1] - 16/6 Y out IOL47[B] LPLL2_C_fb LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
o_led[2] - 17/6 Y out IOL49[A] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
o_led[3] - 18/6 Y out IOL49[B] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
o_led[4] - 19/6 Y out IOL51[A] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
o_led[5] - 20/6 Y out IOL51[B] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
86/0 - in IOT4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/0 - in IOT4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/0 - in IOT6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/0 - in IOT6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
82/0 - in IOT17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/0 - in IOT17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
80/0 - in IOT27[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
79/0 - in IOT27[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
77/1 - in IOT30[A] GCLKT_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
76/1 - in IOT30[B] GCLKC_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
75/1 - in IOT34[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
74/1 - in IOT34[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
73/1 - in IOT40[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
72/1 - in IOT40[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
71/1 - in IOT44[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
70/1 i_uart_rx in IOT44[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
69/1 o_uart_tx out IOT50[A] - LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
25/5 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/5 - in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/5 - in IOB8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/5 - in IOB8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/5 - in IOB14[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
30/5 - in IOB14[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/5 - in IOB18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/5 - in IOB18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/5 - in IOB24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/5 - in IOB24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/4 - in IOB30[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
36/4 - in IOB30[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
37/4 - in IOB34[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/4 - in IOB34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/4 - in IOB40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/4 - in IOB40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/4 - in IOB42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/4 - in IOB43[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1/7 - in IOL3[A] - LVCMOS33 - UP - - - - - - -
p2/7 - in IOL3[B] - LVCMOS33 - UP - - - - - - -
4/7 i_clk in IOL7[A] LPLL1_T_in LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
p5/7 - in IOL8[A] LPLL1_T_fb LVCMOS33 - UP - - - - - - -
p6/7 - in IOL8[B] LPLL1_C_fb LVCMOS33 - UP - - - - - - -
p7/7 - in IOL9[A] - LVCMOS33 - UP - - - - - - -
p8/7 - in IOL9[B] - LVCMOS33 - UP - - - - - - -
p11/7 - in IOL11[A] - LVCMOS33 - UP - - - - - - -
p12/7 - in IOL11[B] - LVCMOS33 - UP - - - - - - -
p14/7 - in IOL12[A] - LVCMOS33 - UP - - - - - - -
p19/7 - in IOL12[B] - LVCMOS33 - UP - - - - - - -
p18/7 - in IOL13[A] - LVCMOS33 - UP - - - - - - -
p21/7 - in IOL13[B] - LVCMOS33 - UP - - - - - - -
p20/7 - in IOL14[A] - LVCMOS33 - UP - - - - - - -
p22/7 - in IOL14[B] - LVCMOS33 - UP - - - - - - -
p23/7 - in IOL15[A] - LVCMOS33 - UP - - - - - - -
p24/7 - in IOL15[B] - LVCMOS33 - UP - - - - - - -
p26/7 - in IOL16[A] - LVCMOS33 - UP - - - - - - -
p28/7 - in IOL16[B] - LVCMOS33 - UP - - - - - - -
p25/7 - in IOL17[A] - LVCMOS33 - UP - - - - - - -
p27/7 - in IOL17[B] - LVCMOS33 - UP - - - - - - -
p29/7 - in IOL18[A] - LVCMOS33 - UP - - - - - - -
p31/7 - in IOL18[B] - LVCMOS33 - UP - - - - - - -
p32/7 - in IOL20[A] - LVCMOS33 - UP - - - - - - -
10/6 - in IOL29[A] GCLKT_6 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
11/6 - in IOL29[B] GCLKC_6 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
p35/6 - in IOL30[A] - LVCMOS33 - UP - - - - - - -
p36/6 - in IOL30[B] - LVCMOS33 - UP - - - - - - -
p37/6 - in IOL35[A] - LVCMOS33 - UP - - - - - - -
p38/6 - in IOL35[B] - LVCMOS33 - UP - - - - - - -
p41/6 - in IOL39[A] - LVCMOS33 - UP - - - - - - -
p42/6 - in IOL39[B] - LVCMOS33 - UP - - - - - - -
13/6 - in IOL45[A] LPLL2_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
15/6 o_led[0] out IOL47[A] LPLL2_T_fb LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
16/6 o_led[1] out IOL47[B] LPLL2_C_fb LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
17/6 o_led[2] out IOL49[A] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
18/6 o_led[3] out IOL49[B] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
19/6 o_led[4] out IOL51[A] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
20/6 o_led[5] out IOL51[B] - LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
p89/2 - in IOR3[A] - LVCMOS33 - UP - - - - - - -
p88/2 - in IOR3[B] - LVCMOS33 - UP - - - - - - -
p85/2 - in IOR4[B] - LVCMOS33 - UP - - - - - - -
p84/2 - in IOR5[A] - LVCMOS33 - UP - - - - - - -
p82/2 - in IOR5[B] - LVCMOS33 - UP - - - - - - -
p83/2 - in IOR6[A] - LVCMOS33 - UP - - - - - - -
p79/2 - in IOR9[A] - LVCMOS33 - UP - - - - - - -
p78/2 - in IOR9[B] - LVCMOS33 - UP - - - - - - -
p76/2 - in IOR11[A] - LVCMOS33 - UP - - - - - - -
p73/2 - in IOR11[B] - LVCMOS33 - UP - - - - - - -
p70/2 - in IOR12[A] - LVCMOS33 - UP - - - - - - -
p68/2 - in IOR12[B] - LVCMOS33 - UP - - - - - - -
p69/2 - in IOR13[A] - LVCMOS33 - UP - - - - - - -
p66/2 - in IOR13[B] - LVCMOS33 - UP - - - - - - -
p67/2 - in IOR14[A] - LVCMOS33 - UP - - - - - - -
p65/2 - in IOR14[B] - LVCMOS33 - UP - - - - - - -
p64/2 - in IOR15[A] - LVCMOS33 - UP - - - - - - -
p61/2 - in IOR15[B] - LVCMOS33 - UP - - - - - - -
p58/2 - in IOR16[A] - LVCMOS33 - UP - - - - - - -
p55/2 - in IOR16[B] - LVCMOS33 - UP - - - - - - -
p59/2 - in IOR17[A] - LVCMOS33 - UP - - - - - - -
p54/2 - in IOR17[B] - LVCMOS33 - UP - - - - - - -
p53/2 - in IOR18[A] - LVCMOS33 - UP - - - - - - -
p52/2 - in IOR18[B] - LVCMOS33 - UP - - - - - - -
8/2 - out IOR25[A] TDO LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
5/2 - in IOR25[B] TMS LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
6/2 - in IOR26[A] TCK LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
7/2 - in IOR26[B] TDI LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
63/3 - in IOR29[A] GCLKT_3 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
88/3 i_rst_n in IOR30[A] MODE0 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
87/3 - in IOR30[B] MODE1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
9/3 - in IOR31[B] RECONFIG_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
62/3 - in IOR33[A] MI/D7 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
61/3 - in IOR33[B] MO/D6 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
60/3 - in IOR34[A] MCS_N/D5 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
59/3 - in IOR34[B] MCLK/D4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
57/3 - in IOR35[A] FASTRD_N/D3 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
56/3 - in IOR36[A] SO/D1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
55/3 - in IOR36[B] SSPI_CS_N/D0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
54/3 - in IOR38[A] DIN/CLKHOLD_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
53/3 - in IOR38[B] DOUT/WE_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
52/3 - in IOR39[A] SCLK LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
p49/3 - in IOR44[A] - LVCMOS33 - UP - - - - - - -
p48/3 - in IOR44[B] - LVCMOS33 - UP - - - - - - -
51/3 - in IOR45[A] RPLL2_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
49/3 - in IOR49[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
48/3 - in IOR49[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3