Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | /Users/car/Projects/hope/alu.v /Users/car/Projects/hope/cpu.v /Users/car/Projects/hope/register_file.v /Users/car/Projects/hope/sequencer.v /Users/car/Projects/hope/sram_srom.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 Education |
| Part Number | GW2AR-LV18QN88C8/I7 |
| Device | GW2AR-18 |
| Device Version | C |
| Created Time | Fri Feb 20 01:45:27 2026 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | cpu |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.041s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 35.484MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.011s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 36.406MB Optimizing Phase 1: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 36.500MB Optimizing Phase 2: CPU time = 0h 0m 0.018s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 37.453MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.011s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 38.266MB Inferring Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.516MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.562MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.625MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.024s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 39.016MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.016MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.016MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 86.234MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.019s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 86.344MB Generate output files: CPU time = 0h 0m 0.029s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 98.953MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 98.953MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 10 |
| I/O Buf | 9 |
| IBUF | 2 |
| OBUF | 6 |
| TBUF | 1 |
| Register | 142 |
| DFF | 2 |
| DFFPE | 6 |
| DFFC | 26 |
| DFFCE | 108 |
| LUT | 1089 |
| LUT2 | 75 |
| LUT3 | 358 |
| LUT4 | 656 |
| ALU | 32 |
| ALU | 32 |
| SSRAM | 12 |
| RAM16SDP4 | 12 |
| INV | 2 |
| INV | 2 |
| DSP | |
| MULT36X36 | 1 |
| BSRAM | 9 |
| SP | 8 |
| pROM | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1195(1091 LUT, 32 ALU, 12 RAM16) / 20736 | 6% |
| Register | 142 / 15750 | <1% |
| --Register as Latch | 0 / 15750 | 0% |
| --Register as FF | 142 / 15750 | <1% |
| BSRAM | 9 / 46 | 20% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | i_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | i_clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | i_clk | 100.000(MHz) | 42.300(MHz) | 23 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -13.641 |
| Data Arrival Time | 23.966 |
| Data Required Time | 10.325 |
| From | microcode_rom_microcode_rom_0_0_s |
| To | microcode_rom_microcode_rom_0_0_s |
| Launch Clk | i_clk[R] |
| Latch Clk | i_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | i_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | microcode_rom_microcode_rom_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 73 | microcode_rom_microcode_rom_0_0_s/DO[11] |
| 3.094 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/I2 |
| 3.547 | 0.453 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/F |
| 4.021 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/I1 |
| 4.576 | 0.555 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/F |
| 5.050 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_init/I0 |
| 5.567 | 0.517 | tINS | FF | 24 | register_file_inst/addr_registers[0]_ER_init/F |
| 6.041 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s2/I0 |
| 6.558 | 0.517 | tINS | FF | 1 | register_file_inst/alu_a_16_s2/F |
| 7.032 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s/I2 |
| 7.485 | 0.453 | tINS | FF | 10 | register_file_inst/alu_a_16_s/F |
| 7.959 | 0.474 | tNET | FF | 1 | alu_inst/n47_s5/I0 |
| 8.476 | 0.517 | tINS | FF | 2 | alu_inst/n47_s5/F |
| 8.950 | 0.474 | tNET | FF | 1 | alu_inst/n49_s3/I1 |
| 9.505 | 0.555 | tINS | FF | 4 | alu_inst/n49_s3/F |
| 9.979 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s10/I1 |
| 10.534 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s10/F |
| 11.008 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s9/I3 |
| 11.379 | 0.371 | tINS | FF | 1 | alu_inst/alu_y_4_s9/F |
| 11.853 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s8/I0 |
| 12.370 | 0.517 | tINS | FF | 1 | alu_inst/alu_y_4_s8/F |
| 12.844 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s7/I1 |
| 13.399 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s7/F |
| 13.873 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s4/I1 |
| 14.428 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s4/F |
| 14.902 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s2/I1 |
| 15.457 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s2/F |
| 15.931 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s0/I3 |
| 16.302 | 0.371 | tINS | FF | 6 | alu_inst/alu_y_4_s0/F |
| 16.776 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s16/I3 |
| 17.147 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s16/F |
| 17.621 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s12/I2 |
| 18.074 | 0.453 | tINS | FF | 1 | sequencer_inst/n27_s12/F |
| 18.548 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s10/I3 |
| 18.919 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s10/F |
| 19.393 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s9/I3 |
| 19.764 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s9/F |
| 20.238 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s6/I3 |
| 20.609 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s6/F |
| 21.083 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s4/I2 |
| 21.536 | 0.453 | tINS | FF | 5 | sequencer_inst/n27_s4/F |
| 22.010 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s3/I2 |
| 22.463 | 0.453 | tINS | FF | 18 | sequencer_inst/n27_s3/F |
| 22.937 | 0.474 | tNET | FF | 1 | sequencer_inst/seq_y_1_s0/I1 |
| 23.492 | 0.555 | tINS | FF | 1 | sequencer_inst/seq_y_1_s0/F |
| 23.966 | 0.474 | tNET | FF | 1 | microcode_rom_microcode_rom_0_0_s/AD[6] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | i_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | microcode_rom_microcode_rom_0_0_s/CLK |
| 10.325 | -0.035 | tSu | 1 | microcode_rom_microcode_rom_0_0_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 10.444, 44.243%; route: 10.902, 46.183%; tC2Q: 2.260, 9.574% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | -13.603 |
| Data Arrival Time | 23.928 |
| Data Required Time | 10.325 |
| From | microcode_rom_microcode_rom_0_0_s |
| To | sequencer_inst/pc_3_s0 |
| Launch Clk | i_clk[R] |
| Latch Clk | i_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | i_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | microcode_rom_microcode_rom_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 73 | microcode_rom_microcode_rom_0_0_s/DO[11] |
| 3.094 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/I2 |
| 3.547 | 0.453 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/F |
| 4.021 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/I1 |
| 4.576 | 0.555 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/F |
| 5.050 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_init/I0 |
| 5.567 | 0.517 | tINS | FF | 24 | register_file_inst/addr_registers[0]_ER_init/F |
| 6.041 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s2/I0 |
| 6.558 | 0.517 | tINS | FF | 1 | register_file_inst/alu_a_16_s2/F |
| 7.032 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s/I2 |
| 7.485 | 0.453 | tINS | FF | 10 | register_file_inst/alu_a_16_s/F |
| 7.959 | 0.474 | tNET | FF | 1 | alu_inst/n47_s5/I0 |
| 8.476 | 0.517 | tINS | FF | 2 | alu_inst/n47_s5/F |
| 8.950 | 0.474 | tNET | FF | 1 | alu_inst/n49_s3/I1 |
| 9.505 | 0.555 | tINS | FF | 4 | alu_inst/n49_s3/F |
| 9.979 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s10/I1 |
| 10.534 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s10/F |
| 11.008 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s9/I3 |
| 11.379 | 0.371 | tINS | FF | 1 | alu_inst/alu_y_4_s9/F |
| 11.853 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s8/I0 |
| 12.370 | 0.517 | tINS | FF | 1 | alu_inst/alu_y_4_s8/F |
| 12.844 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s7/I1 |
| 13.399 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s7/F |
| 13.873 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s4/I1 |
| 14.428 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s4/F |
| 14.902 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s2/I1 |
| 15.457 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s2/F |
| 15.931 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s0/I3 |
| 16.302 | 0.371 | tINS | FF | 6 | alu_inst/alu_y_4_s0/F |
| 16.776 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s16/I3 |
| 17.147 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s16/F |
| 17.621 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s12/I2 |
| 18.074 | 0.453 | tINS | FF | 1 | sequencer_inst/n27_s12/F |
| 18.548 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s10/I3 |
| 18.919 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s10/F |
| 19.393 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s9/I3 |
| 19.764 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s9/F |
| 20.238 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s6/I3 |
| 20.609 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s6/F |
| 21.083 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s4/I2 |
| 21.536 | 0.453 | tINS | FF | 5 | sequencer_inst/n27_s4/F |
| 22.010 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s3/I2 |
| 22.463 | 0.453 | tINS | FF | 18 | sequencer_inst/n27_s3/F |
| 22.937 | 0.474 | tNET | FF | 1 | sequencer_inst/n32_s0/I0 |
| 23.454 | 0.517 | tINS | FF | 1 | sequencer_inst/n32_s0/F |
| 23.928 | 0.474 | tNET | FF | 1 | sequencer_inst/pc_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | i_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | sequencer_inst/pc_3_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | sequencer_inst/pc_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 10.406, 44.153%; route: 10.902, 46.258%; tC2Q: 2.260, 9.589% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | -13.603 |
| Data Arrival Time | 23.928 |
| Data Required Time | 10.325 |
| From | microcode_rom_microcode_rom_0_0_s |
| To | sequencer_inst/pc_5_s0 |
| Launch Clk | i_clk[R] |
| Latch Clk | i_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | i_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | microcode_rom_microcode_rom_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 73 | microcode_rom_microcode_rom_0_0_s/DO[11] |
| 3.094 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/I2 |
| 3.547 | 0.453 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/F |
| 4.021 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/I1 |
| 4.576 | 0.555 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/F |
| 5.050 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_init/I0 |
| 5.567 | 0.517 | tINS | FF | 24 | register_file_inst/addr_registers[0]_ER_init/F |
| 6.041 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s2/I0 |
| 6.558 | 0.517 | tINS | FF | 1 | register_file_inst/alu_a_16_s2/F |
| 7.032 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s/I2 |
| 7.485 | 0.453 | tINS | FF | 10 | register_file_inst/alu_a_16_s/F |
| 7.959 | 0.474 | tNET | FF | 1 | alu_inst/n47_s5/I0 |
| 8.476 | 0.517 | tINS | FF | 2 | alu_inst/n47_s5/F |
| 8.950 | 0.474 | tNET | FF | 1 | alu_inst/n49_s3/I1 |
| 9.505 | 0.555 | tINS | FF | 4 | alu_inst/n49_s3/F |
| 9.979 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s10/I1 |
| 10.534 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s10/F |
| 11.008 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s9/I3 |
| 11.379 | 0.371 | tINS | FF | 1 | alu_inst/alu_y_4_s9/F |
| 11.853 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s8/I0 |
| 12.370 | 0.517 | tINS | FF | 1 | alu_inst/alu_y_4_s8/F |
| 12.844 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s7/I1 |
| 13.399 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s7/F |
| 13.873 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s4/I1 |
| 14.428 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s4/F |
| 14.902 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s2/I1 |
| 15.457 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s2/F |
| 15.931 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s0/I3 |
| 16.302 | 0.371 | tINS | FF | 6 | alu_inst/alu_y_4_s0/F |
| 16.776 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s16/I3 |
| 17.147 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s16/F |
| 17.621 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s12/I2 |
| 18.074 | 0.453 | tINS | FF | 1 | sequencer_inst/n27_s12/F |
| 18.548 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s10/I3 |
| 18.919 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s10/F |
| 19.393 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s9/I3 |
| 19.764 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s9/F |
| 20.238 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s6/I3 |
| 20.609 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s6/F |
| 21.083 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s4/I2 |
| 21.536 | 0.453 | tINS | FF | 5 | sequencer_inst/n27_s4/F |
| 22.010 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s3/I2 |
| 22.463 | 0.453 | tINS | FF | 18 | sequencer_inst/n27_s3/F |
| 22.937 | 0.474 | tNET | FF | 1 | sequencer_inst/n30_s0/I0 |
| 23.454 | 0.517 | tINS | FF | 1 | sequencer_inst/n30_s0/F |
| 23.928 | 0.474 | tNET | FF | 1 | sequencer_inst/pc_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | i_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | sequencer_inst/pc_5_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | sequencer_inst/pc_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 10.406, 44.153%; route: 10.902, 46.258%; tC2Q: 2.260, 9.589% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | -13.603 |
| Data Arrival Time | 23.928 |
| Data Required Time | 10.325 |
| From | microcode_rom_microcode_rom_0_0_s |
| To | sequencer_inst/pc_6_s0 |
| Launch Clk | i_clk[R] |
| Latch Clk | i_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | i_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | microcode_rom_microcode_rom_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 73 | microcode_rom_microcode_rom_0_0_s/DO[11] |
| 3.094 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/I2 |
| 3.547 | 0.453 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/F |
| 4.021 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/I1 |
| 4.576 | 0.555 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/F |
| 5.050 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_init/I0 |
| 5.567 | 0.517 | tINS | FF | 24 | register_file_inst/addr_registers[0]_ER_init/F |
| 6.041 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s2/I0 |
| 6.558 | 0.517 | tINS | FF | 1 | register_file_inst/alu_a_16_s2/F |
| 7.032 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s/I2 |
| 7.485 | 0.453 | tINS | FF | 10 | register_file_inst/alu_a_16_s/F |
| 7.959 | 0.474 | tNET | FF | 1 | alu_inst/n47_s5/I0 |
| 8.476 | 0.517 | tINS | FF | 2 | alu_inst/n47_s5/F |
| 8.950 | 0.474 | tNET | FF | 1 | alu_inst/n49_s3/I1 |
| 9.505 | 0.555 | tINS | FF | 4 | alu_inst/n49_s3/F |
| 9.979 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s10/I1 |
| 10.534 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s10/F |
| 11.008 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s9/I3 |
| 11.379 | 0.371 | tINS | FF | 1 | alu_inst/alu_y_4_s9/F |
| 11.853 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s8/I0 |
| 12.370 | 0.517 | tINS | FF | 1 | alu_inst/alu_y_4_s8/F |
| 12.844 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s7/I1 |
| 13.399 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s7/F |
| 13.873 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s4/I1 |
| 14.428 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s4/F |
| 14.902 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s2/I1 |
| 15.457 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s2/F |
| 15.931 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s0/I3 |
| 16.302 | 0.371 | tINS | FF | 6 | alu_inst/alu_y_4_s0/F |
| 16.776 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s16/I3 |
| 17.147 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s16/F |
| 17.621 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s12/I2 |
| 18.074 | 0.453 | tINS | FF | 1 | sequencer_inst/n27_s12/F |
| 18.548 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s10/I3 |
| 18.919 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s10/F |
| 19.393 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s9/I3 |
| 19.764 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s9/F |
| 20.238 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s6/I3 |
| 20.609 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s6/F |
| 21.083 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s4/I2 |
| 21.536 | 0.453 | tINS | FF | 5 | sequencer_inst/n27_s4/F |
| 22.010 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s3/I2 |
| 22.463 | 0.453 | tINS | FF | 18 | sequencer_inst/n27_s3/F |
| 22.937 | 0.474 | tNET | FF | 1 | sequencer_inst/n29_s0/I0 |
| 23.454 | 0.517 | tINS | FF | 1 | sequencer_inst/n29_s0/F |
| 23.928 | 0.474 | tNET | FF | 1 | sequencer_inst/pc_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | i_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | sequencer_inst/pc_6_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | sequencer_inst/pc_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 10.406, 44.153%; route: 10.902, 46.258%; tC2Q: 2.260, 9.589% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | -13.603 |
| Data Arrival Time | 23.928 |
| Data Required Time | 10.325 |
| From | microcode_rom_microcode_rom_0_0_s |
| To | sequencer_inst/pc_7_s0 |
| Launch Clk | i_clk[R] |
| Latch Clk | i_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | i_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | microcode_rom_microcode_rom_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 73 | microcode_rom_microcode_rom_0_0_s/DO[11] |
| 3.094 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/I2 |
| 3.547 | 0.453 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s44/F |
| 4.021 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/I1 |
| 4.576 | 0.555 | tINS | FF | 1 | register_file_inst/addr_registers[0]_ER_CL_s41/F |
| 5.050 | 0.474 | tNET | FF | 1 | register_file_inst/addr_registers[0]_ER_init/I0 |
| 5.567 | 0.517 | tINS | FF | 24 | register_file_inst/addr_registers[0]_ER_init/F |
| 6.041 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s2/I0 |
| 6.558 | 0.517 | tINS | FF | 1 | register_file_inst/alu_a_16_s2/F |
| 7.032 | 0.474 | tNET | FF | 1 | register_file_inst/alu_a_16_s/I2 |
| 7.485 | 0.453 | tINS | FF | 10 | register_file_inst/alu_a_16_s/F |
| 7.959 | 0.474 | tNET | FF | 1 | alu_inst/n47_s5/I0 |
| 8.476 | 0.517 | tINS | FF | 2 | alu_inst/n47_s5/F |
| 8.950 | 0.474 | tNET | FF | 1 | alu_inst/n49_s3/I1 |
| 9.505 | 0.555 | tINS | FF | 4 | alu_inst/n49_s3/F |
| 9.979 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s10/I1 |
| 10.534 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s10/F |
| 11.008 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s9/I3 |
| 11.379 | 0.371 | tINS | FF | 1 | alu_inst/alu_y_4_s9/F |
| 11.853 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s8/I0 |
| 12.370 | 0.517 | tINS | FF | 1 | alu_inst/alu_y_4_s8/F |
| 12.844 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s7/I1 |
| 13.399 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s7/F |
| 13.873 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s4/I1 |
| 14.428 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s4/F |
| 14.902 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s2/I1 |
| 15.457 | 0.555 | tINS | FF | 1 | alu_inst/alu_y_4_s2/F |
| 15.931 | 0.474 | tNET | FF | 1 | alu_inst/alu_y_4_s0/I3 |
| 16.302 | 0.371 | tINS | FF | 6 | alu_inst/alu_y_4_s0/F |
| 16.776 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s16/I3 |
| 17.147 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s16/F |
| 17.621 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s12/I2 |
| 18.074 | 0.453 | tINS | FF | 1 | sequencer_inst/n27_s12/F |
| 18.548 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s10/I3 |
| 18.919 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s10/F |
| 19.393 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s9/I3 |
| 19.764 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s9/F |
| 20.238 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s6/I3 |
| 20.609 | 0.371 | tINS | FF | 1 | sequencer_inst/n27_s6/F |
| 21.083 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s4/I2 |
| 21.536 | 0.453 | tINS | FF | 5 | sequencer_inst/n27_s4/F |
| 22.010 | 0.474 | tNET | FF | 1 | sequencer_inst/n27_s3/I2 |
| 22.463 | 0.453 | tINS | FF | 18 | sequencer_inst/n27_s3/F |
| 22.937 | 0.474 | tNET | FF | 1 | sequencer_inst/n28_s0/I0 |
| 23.454 | 0.517 | tINS | FF | 1 | sequencer_inst/n28_s0/F |
| 23.928 | 0.474 | tNET | FF | 1 | sequencer_inst/pc_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | i_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | i_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 163 | i_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | sequencer_inst/pc_7_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | sequencer_inst/pc_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 10.406, 44.153%; route: 10.902, 46.258%; tC2Q: 2.260, 9.589% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |